1. Field of the Invention
The present invention relates to a power amplifier, and more particularly, to a cascode power amplifier and a method for controlling a cascode power amplifier.
2. Description of the Prior Art
Due to each communication system has its own signal modulation method, a power emitter built in the communication system has a unique specification. Power amplifiers with higher linearity are usually required because the orthogonal frequency division multiplexing (OFDM) modulation signals adopted by standards 802.11a, 802.11b and 802.11g have a high peak-to-average power ratio (PAPR). In addition, the high PAPR signal will damage transistors of the power amplifier due to hot carrier impact and oxide layer breakdown, causing the life cycles of the transistors to be reduced and often resulting in permanent damage. Therefore, it is preferable that the power amplifier have a cascode structure to prevent its transistors from being damaged by a high voltage.
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a prior art cascode power amplifier 100. As shown in FIG. 1, the cascode power amplifier 100 is used for amplifying an input signal Vin to output an output signal Vout. The cascode power amplifier 100 comprises transistors M1 and M2, an inductor L and a capacitor C serving as loadings. To assure that the transistors M1 and M2 can operate in a saturation region, a gate electrode of the transistor M2 is connected to a supply voltage VDD. In addition, the transistor M1 is a core device to make the caocode power amplifier have a better frequency response, and the transistor M2 is an input/output (I/O) device for sustaining a high output voltage Vout. Because a tolerance of the core device is small (1.2V, for example), a voltage level of a drain electrode of the transistor M1 (i.e. the node N1 shown in FIG. 1) may exceed the tolerance of the transistor M1 when the cascode power amplifier 100 is supplied by a greater supply voltage VDD. That could damage gate-drain capacitance Cgd and drain-source capacitance Cds of the transistor M1, and therefore influences the reliability of the transistor M1.
To solve the above-mentioned problem with regards to the reliability of the transistor M1 being influenced due to an over-high voltage at the node N1, a prior art method reduces a channel width of the transistor M2 in order to lower the voltage at the node N1. Reducing the channel width, however, will lower a trans-conductance of the transistor M2, meaning the gain of the cascode power amplifier 100 is also lowered due to a heavier miller effect of the transistor M1.
In addition, because the gate electrode of the transistor M2 is connected to the supply voltage VDD, a swing of the output signal Vout of the cascode power amplifier 100 is limited to be less than a threshold voltage Vth2 of the transistor M2. When the swing of the output signal Vout of the cascode power amplifier 100 is greater than the threshold voltage Vth2, the transistor M2 operates in a triode region and the output signal Vout is distorted. Furthermore, a drain-base junction of the transistor M2 may be damaged when the cascode power amplifier 100 is working due to the connection between a base electrode of the transistor M2 and a ground voltage GND.